Single Carrier Trapping and De-trapping in Scaled Silicon Complementary Metal-Oxide-Semiconductor Field-Effect Transistors at Low Temperatures

The scaling of Silicon (Si) technology is approaching the physical limit, where various quantum effects such as direct tunnelling and quantum confinement are observed, even at room temperatures. We have measured standard Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (CMOSFETs) with wide and short channels at low temperatures to observe single electron/hole characteristics due to local structural disturbances such as roughness and defects. In fact, we observed Coulomb blockades in sub-threshold regimes of both p-type and n-type Si CMOSFETs, showing the presence of quantum dots in the channels. The stability diagrams for the Coulomb blockade were explained by the potential minima due to poly-Si grains. We have also observed sharp current peaks at narrow bias windows at the edges of the Coulomb diamonds, showing resonant tunnelling of single carriers through charge traps. Single Carrier Trapping and De-trapping in Scaled Silicon Complementary Metal-Oxide-Semiconductor Field-Effect Transistors at Low Temperatures2